In the conventional semiconductor packages, leadframes are widely implemented as chip carriers and electrical media where bonding wires are used as internal electrical connections and encapsulant is used to encapsulate the chips and the bonding wires. For multi-chip semiconductor packages, the arrangement of the multiple chips can be divided into side-by-side arrangement and stacked arrangement where the side-by-side arrangement is to individually attach a plurality of chips (or called as dice) onto a leadframe and is suitable for the semiconductor package with limited heights. However, when the chip thicknesses are different, the thicker chip will make the top molding gap from the top surface of the thicker chip to the top surface of the encapsulant to be smaller causing a larger gap ratio of the bottom molding gap to the top molding gap leading to different filling speeds between the bottom molding gap and the top molding gap during encapsulation where encapsulated voids will easily be formed during the molding processes. Furthermore, since the top molding gap becomes smaller, the bonding wires will be easily exposed from the encapsulant leading to lower assembling yields of the side-by-side arranged multi-chip semiconductor packages. Moreover, the encapsulant volumes above and below the chips will be different leading to warpage issues of the semiconductor packages.